1. Technical Field
The present invention relates to wafer testing, and more specifically, to probing pads on wafer for wafer testing.
2. Related Art
In a conventional semiconductor fabrication process, multiple semiconductor chips (i.e., integrated circuits) can be fabricated on the same wafer. Each of the chips comprises bond pads on the chip's perimeter which provide electrical access to underlying devices of the chip. During packaging of the chip after chip dicing, each of these bond pads is physically bonded to a wire (assuming wire bonding technology is used for forming connections between the bond pads and the package enclosing the chip). The wire itself is physically connected to a package pin of the package via an inner lead line of the package. The vast majority of chips will be tested at wafer test. Conventionally, wafer testing uses the bond pads to electrically access the devices of the chips. This results in the bond pads being damaged, which is undesirable for the assembly process.
As a result, there is a need for a structure (and a method for forming the same) in which wafer testing is performed without damaging the bond pads.